Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
In recent years, and as channel lengths are being scaled below 0.1 μm, SOI complementary metal oxide semiconductor (CMOS) technology has received considerable interest in VLSI for its potential low-voltage, low-power, and high-speed advantages in comparison to bulk CMOS devices. As known to those skilled in the art, SOI structures include an insulating layer, i.e., buried oxide region (BOX), that electrically isolates a top Si-containing layer from a bottom Si-containing layer. The top Si-containing, i.e., the SOI layer, serves as the area in which electronic devices such as CMOS devices can be fabricated.
Thin film SOI CMOS devices, such as SOI MOSFETs, in which the top Si-containing layer has a thickness of about 20 nm or less, are of special interest due to improved isolation, reduced parasitic capacitance as well as the reduction of short-channel and floating body effects that can be obtained from such technology. Despite the known advantages with thin film SOI technology, processing challenges exist which substantially hamper the use of thin SOI MOSFETs in semiconductor integrated circuits. For example, prior art processes for fabricating SOI MOSFETs have difficulty in forming a thin (20 nm or less) SOI channel region. One prior art technique to obtain very thin SOI channels is to recess the channel while protecting the S/D regions. This prior art technique ensures that the series resistance of the device can be kept small since the S/D regions can be made as thick as desired. However, in existing recessed channel technology, it is difficult to form extension and halo implant regions having abrupt, i.e., sharp, lateral profiles that overlap the gate edges.
In view of the above-mentioned drawbacks with fabricating prior art thin SOI MOSFETs, there exists a need for providing a new and improved method for fabricating recessed channel MOSFETs which have a thin SOI device channel region as well as adjoining extension and halo implant regions having abrupt lateral profiles that overlap the edges of the gate region.